This invention relates to acquiring data, and, more particularly, to an apparatus and method for acquiring data in a shift register that is used to store data representing occurrence times of events and for detecting when that data has become stale.
A time-to-digital converter (TDC) is used to capture the time at which an event occurs, that is, to convert an occurrence time into digital timing data. A typical application is in particle physics experimentation in which a system of detectors is instrumented so as to produce detection signals supplied to individual channels of the TDC in response to the occurrence of events, such as sub-atomic particles colliding with nuclei. Unfortunately, in addition to desired experimental data signals, unwanted signals are generated from real events not of interest and from background events such as neutron interactions and cosmic rays. Events not of interest often occur well before or after events of interest, so that if an event is captured well before an event of interest, data related thereto generally is stale by the time the event of interest occurs.
Event capture is done by setting a TDC to operate in either "common start" or "common stop" mode. In common start mode, a common start signal is supplied to start a time counter used with all channels, which is stopped, that is, the time count is captured, when an event, or hit, arrives at the channel. In common stop mode, the time counter is started in each channel by the arrival of a hit, and time count capture is effected upon the arrival of a common stop signal supplied simultaneously to all channels. Common stop mode is preferred when large numbers of detectors are used, as is usual in modern experiments, because less cabling and less inter-channel signal synchronization are required than when common start mode is used.
In older TDCs, the time counter is a charging capacitor, where time is determined from charge level. However, such an analog time counter introduces linearity difficulties, that is, distortion in the time. In newer TDCs, a crystal controlled digital time counter is used, but this counter presents difficulties in timing resolution, that is, the duration in nanoseconds (10.sup.-9 seconds) of a timing count, and in dynamic range, that is, the largest number of timing counts that can be distinguished.
Conventional single hit TDCs are provided with a limited capacity to capture one event per channel. However, these TDCs permit a desired event to be hidden by stale data.
Newer TDCs have multi-hit channels, that is, channels which have a higher storage capacity sufficient to capture many events per channel. Two techniques generally are used in digital multi-hit TDCs: clocking of a shift register and writing the value of a counter to memory.
An example of a multi-hit shift register TDC is the LeCroy Model 1879 Pipeline TDC described at page 63 of the 1990 Research Instrumentation Catalog of the LeCroy Corporation, the assignee of the present invention. The Model 1879 TDC includes a 512 element shift register whose contents are shifted at every clock pulse. The absence of a hit in a channel during a clock pulse is indicated by one value, such a logical "0" and the presence of a hit is indicated by another value, such as logical "1". Each of the 512 values is read out for subsequent data analysis. Drawbacks of this approach are that the dynamic range is limited to 512 clock pulses, and that, since the TDC is unavailable for data capture during read out, the period of unavailability is extended by read out of values indicating absence of events.
Multi-hit TDCs in which a time count is Written to a memory are limited to common start applications due to counter roll-over. That is, common stop mode cannot be used when writing time counts to memory because of the inability to distinguish stale data in memory.
Conventional techniques for identifying stale data are known in the computer cache memory field For example, U.S. Pat. No. 4,168,541 (DeKarske) uses a set of three age bits per four blocks to identify a data block which should be replaced with a new block of data from a main memory; this technique is inappropriate for use in a TDC since it measures age as least recent usage of a data block rather than measuring age as cumulative timing counts. In U.S. Pat. No. 4,747,043 (Rodman), a flag bit is used to indicate whether a word stored in a cache memory is invalid because its corresponding word in the main memory has been changed; this technique is inappropriate for use in a TDC since it is concerned with keeping two memories synchronized, rather than disposing of stale data in one memory after a predetermined residence duration.